This page (revision-4) was last changed on 03-Feb-2023 15:21 by Florian Dingler 

This page was created on 11-Oct-2015 20:34 by Florian Dingler

Only authorized users are allowed to rename pages.

Only authorized users are allowed to delete pages.

Page revision history

Version Date Modified Size Author Changes ... Change note
4 03-Feb-2023 15:21 722 bytes Florian Dingler to previous
3 24-Feb-2019 17:41 722 bytes Florian Dingler to previous | to last
2 21-Mar-2017 23:07 708 bytes Florian Dingler to previous | to last
1 11-Oct-2015 20:34 670 bytes Florian Dingler to last

Page References

Incoming links Outgoing links
PBCTL
PBCTL

Version management

Difference between version and

At line 10 changed one line
|2|PA2|1=use Port A for data input/output, 0=define data direction, see below
|2|PA2|1=use Port B for data input/output, 0=define data direction, see below
At line 14 changed one line
To define the data direction of PORT B, set Bit 2 of PBCTL to 0. Then write a byte to [PORTB], where Bits set to 1 indicate WRITE and Bits set to 0 indicate READ. Normally PORTB is set to %00000000 (=all input).
To define the data direction of PORT B, set Bit 2 of [PBCTL] to 0. Then write a byte to [PORTB], where Bits set to 1 indicate WRITE and Bits set to 0 indicate READ. Normally [PORTB] is set to %00000000 (=all input).
At line 18 added 4 lines
previous: [PACTL]
next: [DMACTL] of ANTIC
This page (revision-4) was last changed on 03-Feb-2023 15:21 by Florian Dingler  Top