||Read/Write||ADR||HEXADR||NAME||Description||OS
|Read|53768|$D208|ALLPOT|Audio control|all
|Write|53768|$D208|AUDCTL|Pot Port State|all

!!!AUDCTL (Write)
AUDCTL is the option byte which affects all sound channels. This bit assignment is:
||Bit||Description
|7|	Makes the 17 bit poly counter into nine bit poly 
|6|	Clock channel one with 1.79 MHz 
|5|	Clock channel three with 1.79 MHz 
|4|	Join channels two and one (16 bit) 
|3|	Join channels four and three (16 bit) 
|2|	Insert high pass filter into channel one, clocked by channel two 
|1|	Insert high pass filter into channel two, clocked by channel four 
|0|	Switch main clock base from 64 KHz to 15 KHz to be done

!!!ALLPOT (Read)
Shows if the readings of the pots are (already) valid.
||Bit||Paddle||Shadow||Register
|0|Paddle 0| [PADDL0]| [POT0]
|1|Paddle 1| [PADDL1]| [POT1]
|2|Paddle 2| [PADDL2]| [POT2]
|3|Paddle 3| [PADDL3]| [POT3]
|4|Paddle 4| [PADDL4]| [POT4]
|5|Paddle 5| [PADDL5]| [POT5]
|6|Paddle 6| [PADDL6]| [POT6]
|7|Paddle 7| [PADDL7]| [POT7]
If a bit equals zero (0), then the register value for that pot (e.g. Bit 0 = [POT0]) is valid; if the Bit is one (1), then the value is not (yet) valid, because the reading/scan is not finished yet or there is no paddle connected.

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see also: [Controller topics|Controller_topics], [POTGO], [ALLPOT], [SKCTL]

previous: [AUDC4],[POT7]

next: [STIMER]