This page (revision-14) was last changed on 03-Feb-2023 15:21 by Stefan Haubenthal 

This page was created on 20-Mar-2010 15:29 by Florian Dingler

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Page revision history

Version Date Modified Size Author Changes ... Change note
14 03-Feb-2023 15:21 6 KB Stefan Haubenthal to previous
13 23-Jul-2010 16:45 6 KB Stefan Haubenthal to previous | to last Zeile verrutscht
12 23-Jul-2010 12:46 6 KB Gromit to previous | to last
11 21-Mar-2010 11:47 6 KB Florian Dingler to previous | to last
10 21-Mar-2010 11:39 4 KB Florian Dingler to previous | to last
9 21-Mar-2010 11:32 3 KB Florian Dingler to previous | to last
8 20-Mar-2010 20:45 2 KB Florian Dingler to previous | to last
7 20-Mar-2010 16:03 2 KB Florian Dingler to previous | to last
6 20-Mar-2010 15:52 1 KB Florian Dingler to previous | to last
5 20-Mar-2010 15:51 1 KB Florian Dingler to previous | to last
4 20-Mar-2010 15:47 1 KB Florian Dingler to previous | to last
3 20-Mar-2010 15:40 1 KB Florian Dingler to previous | to last
2 20-Mar-2010 15:37 1 KB Florian Dingler to previous | to last
1 20-Mar-2010 15:29 831 bytes Florian Dingler to last

Page References

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Connectors
Connectors

Version management

Difference between version and

At line 93 changed one line
!Cartridge
!(Left) Cartridge
At line 102 changed one line
|1. _S4 Chip Select--$8000 to $9FFF |A. RD4 ROM present- $8000 to $9FFF
|1. _S4 Chip Select $8000 to $9FFF |A. RD4 ROM present $8000 to $9FFF
At line 113 changed one line
|12. _S5 Chip Select--$A000 to $BFFF |N. A11 CPU Address bus line
|12. _S5 Chip Select $A000 to $BFFF |N. A11 CPU Address bus line
At line 115 changed one line
|14. RD5 ROM present--$A000 to $BFFF |R. _R/W CPU read/write
|14. RD5 ROM present $A000 to $BFFF |R. R/_W CPU read/write
At line 119 added 25 lines
!Right Cartridge (800 only)
{{{
A B C D E F H J K L M N P R S
o o o o o o o o o o o o o o o
o o o o o o o o o o o o o o o
1 15
}}}
||upper row||lower row
|1. R/_W CPU read/write late |A. B02,Phi2 CPU Phase 2 clock
|2. A3 CPU Address bus line |B. GND Ground
|3. A2 CPU Address bus line |C. A4 CPU Address bus line
|4. A1 CPU Address bus line |D. A5 CPU Address bus line
|5. A0 CPU Address bus line |E. A6 CPU Address bus line
|6. D4 CPU Data bus line |F. A7 CPU Address bus line
|7. D5 CPU Data bus line |H. A8 CPU Address bus line
|8. D2 CPU Data bus line |J. A9 CPU Address bus line
|9. D1 CPU Data bus line |K. A12 CPU Address bus line
|10. D0 CPU Data bus line |L. D3 CPU Data bus line
|11. D6 CPU Data bus line |M. D7 CPU Data bus line
|12. _S4 Chip Select--$8000 to $9FFF |N. A11 CPU Address bus line
|13. +5V |P. A10 CPU Address bus line
|14. RD4 ROM present--$8000 to $9FFF |R. R/_W Read/write
|15. _CCTL Cartridge control select |S. B02,Phi2 CPU Phase 2 clock
_=active low
This page (revision-14) was last changed on 03-Feb-2023 15:21 by Stefan Haubenthal  Top