This page (revision-14) was last changed on 03-Feb-2023 15:21 by Stefan Haubenthal 

This page was created on 20-Mar-2010 15:29 by Florian Dingler

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Version Date Modified Size Author Changes ... Change note
14 03-Feb-2023 15:21 6 KB Stefan Haubenthal to previous
13 23-Jul-2010 16:45 6 KB Stefan Haubenthal to previous | to last Zeile verrutscht
12 23-Jul-2010 12:46 6 KB Gromit to previous | to last
11 21-Mar-2010 11:47 6 KB Florian Dingler to previous | to last
10 21-Mar-2010 11:39 4 KB Florian Dingler to previous | to last
9 21-Mar-2010 11:32 3 KB Florian Dingler to previous | to last
8 20-Mar-2010 20:45 2 KB Florian Dingler to previous | to last
7 20-Mar-2010 16:03 2 KB Florian Dingler to previous | to last
6 20-Mar-2010 15:52 1 KB Florian Dingler to previous | to last
5 20-Mar-2010 15:51 1 KB Florian Dingler to previous | to last
4 20-Mar-2010 15:47 1 KB Florian Dingler to previous | to last
3 20-Mar-2010 15:40 1 KB Florian Dingler to previous | to last
2 20-Mar-2010 15:37 1 KB Florian Dingler to previous | to last
1 20-Mar-2010 15:29 831 bytes Florian Dingler to last

Page References

Incoming links Outgoing links
Connectors
Connectors

Version management

Difference between version and

At line 144 changed one line
!Enhanced Cartridge Interface (ECI)/Expansion port (130XE, 800XE, & later 65XE)
!Enhanced Cartridge Interface (ECI)/Expansion port
only on 130XE, 800XE and later 65XE versions
At line 161 changed 2 lines
!Parallel Bus
to be added
!Parallel Bus Interface (PBI)
only on 600XL and 800XL
{{{
1 49
o o o o o o o o o o o o o o o o o o o o o o o o o (upper side of PCB)
o o o o o o o o o o o o o o o o o o o o o o o o o (lower side of PCB)
2 50
}}}
||upper row||lower row
|1. GND Ground |2. _EXTSEL External Select
|3. A0 CPU Address bus line |4. A1 CPU Address bus line
|5. A2 CPU Address bus line |6. A3 CPU Address bus line
|7. A4 CPU Address bus line |8. A5 CPU Address bus line
|9. A6 CPU Address bus line |10. GND Ground
|11. A7 CPU Address bus line |12. A8 CPU Address bus line
|13. A9 CPU Address bus line |14. A10 CPU Address bus line
|15. A11 CPU Address bus line |16. A12 CPU Address bus line
|17. A13 CPU Address bus line |18. A14 CPU Address bus line
|19. GND Ground |20. A15 CPU Address bus line
|21. D0 CPU Data bus line |22. D1 CPU Data bus line
|23. D2 CPU Data bus line |24. D3 CPU Data bus line
|25. D4 CPU Data bus line |26. D5 CPU Data bus line
|27. D6 CPU Data bus line |28. D7 CPU Data bus line
|29. GND Ground |30. GND Ground
|31. B02,Phi2 CPU Phase 2 clock |32. GND Ground
|33. NC Reserved |34. _RST Reset output
|35. _IRQ Interrupt request |36. _RDY Ready input
|37. NC Reserved |38. _EXTENB CPU External decoder Enable
|39. NC Reserved |40. _REF Refresh cycle
|41. _CAS Column Address Strobe |42. GND Ground
|43. _MPD Math Pack (FP) Disable |44. _RAS Row Address Strobe
|45. GND Ground |46. LR/_W Latched read/write
|47. 800XL: NC. 600XL: +5V |48. 800XL: NC. 600XL: +5V
|49. Audio input |50. GND Ground
_=active low
----
with information from:
* [http://www.faqs.org/faqs/atari-8-bit/faq/]
* [http://www.hardwarebook.info/]
This page (revision-14) was last changed on 03-Feb-2023 15:21 by Stefan Haubenthal  Top