At line 15 changed 2 lines |
|7 ~Command|8 Motor control |
|9 ~Proceed |10 +5V DC/Ready |
|7 _Command|8 Motor control |
|9 _Proceed |10 +5V DC/Ready |
At line 18 changed one line |
|13 ~Interrupt |
|13 _Interrupt |
At line 21 changed one line |
* ~=active low |
* _=active low |
At line 42 changed one line |
6 see [STRIG0]-[STRIG3], also Light Pen Input, see [LPENV], [LPENH] |
6 see [STRIG0]-[STRIG3], also Light Pen Input, see [LPENV], [LPENH], (400 supports a light pen or light gun in port 4 only)\\ |
7 +5V |
At line 92 changed 2 lines |
!Cartridge |
to be added |
!(Left) Cartridge |
on all machines; "Left Cartridge" on 800 |
{{{ |
A B C D E F H J K L M N P R S |
o o o o o o o o o o o o o o o |
o o o o o o o o o o o o o o o |
1 15 |
}}} |
||upper row||lower row |
|1. _S4 Chip Select $8000 to $9FFF |A. RD4 ROM present $8000 to $9FFF |
|2. A3 CPU Address bus line |B. GND Ground |
|3. A2 CPU Address bus line |C. A4 CPU Address bus line |
|4. A1 CPU Address bus line |D. A5 CPU Address bus line |
|5. A0 CPU Address bus line |E. A6 CPU Address bus line |
|6. D4 CPU Data bus line |F. A7 CPU Address bus line |
|7. D5 CPU Data bus line |H. A8 CPU Address bus line |
|8. D2 CPU Data bus line |J. A9 CPU Address bus line |
|9. D1 CPU Data bus line |K. A12 CPU Address bus line |
|10. D0 CPU Data bus line |L. D3 CPU Data bus line |
|11. D6 CPU Data bus line |M. D7 CPU Data bus line |
|12. _S5 Chip Select $A000 to $BFFF |N. A11 CPU Address bus line |
|13. +5V |P. A10 CPU Address bus line |
|14. RD5 ROM present $A000 to $BFFF |R. R/_W CPU read/write |
|15. _CCTL Cartridge control select |S. B02,Phi2 CPU Phase 2 clock |
_=active low |
At line 95 changed one line |
!Enhanced Cartridge Interface (ECI)/Expansion port (130XE, 800XE, & later 65XE) |
!Right Cartridge (800 only) |
At line 121 added 26 lines |
A B C D E F H J K L M N P R S |
o o o o o o o o o o o o o o o |
o o o o o o o o o o o o o o o |
1 15 |
}}} |
||upper row||lower row |
|1. R/_W CPU read/write late |A. B02,Phi2 CPU Phase 2 clock |
|2. A3 CPU Address bus line |B. GND Ground |
|3. A2 CPU Address bus line |C. A4 CPU Address bus line |
|4. A1 CPU Address bus line |D. A5 CPU Address bus line |
|5. A0 CPU Address bus line |E. A6 CPU Address bus line |
|6. D4 CPU Data bus line |F. A7 CPU Address bus line |
|7. D5 CPU Data bus line |H. A8 CPU Address bus line |
|8. D2 CPU Data bus line |J. A9 CPU Address bus line |
|9. D1 CPU Data bus line |K. A12 CPU Address bus line |
|10. D0 CPU Data bus line |L. D3 CPU Data bus line |
|11. D6 CPU Data bus line |M. D7 CPU Data bus line |
|12. _S4 Chip Select--$8000 to $9FFF |N. A11 CPU Address bus line |
|13. +5V |P. A10 CPU Address bus line |
|14. RD4 ROM present--$8000 to $9FFF |R. R/_W Read/write |
|15. _CCTL Cartridge control select |S. B02,Phi2 CPU Phase 2 clock |
_=active low |
|
!Enhanced Cartridge Interface (ECI)/Expansion port |
only on 130XE, 800XE and later 65XE versions |
{{{ |
At line 103 changed 4 lines |
|A. Reserved | 1. EXTSEL' External Select |
|B. IRQ' Interrupt request | 2. RST' Reset output |
|C. HALT' Halt CPU |3. D1XX' Chip select at area $D1xx |
|D. A13 CPU Address bus line | 4. MPD' Math Pack (FP) Disable |
|A. Reserved | 1. _EXTSEL External Select |
|B. _IRQ Interrupt request | 2. _RST Reset output |
|C. _HALT Halt CPU |3. _D1XX Chip select at area $D1xx |
|D. A13 CPU Address bus line | 4. _MPD Math Pack (FP) Disable |
At line 108 changed one line |
|F. A15 CPU Address bus line | 6. REF' Refresh cycle |
|F. A15 CPU Address bus line | 6. _REF Refresh cycle |
At line 160 added one line |
_=active low |
At line 111 changed 2 lines |
!Parallel Bus |
to be added |
!Parallel Bus Interface (PBI) |
only on 600XL and 800XL |
{{{ |
1 49 |
o o o o o o o o o o o o o o o o o o o o o o o o o (upper side of PCB) |
o o o o o o o o o o o o o o o o o o o o o o o o o (lower side of PCB) |
2 50 |
}}} |
||upper row||lower row |
|1. GND Ground |2. _EXTSEL External Select |
|3. A0 CPU Address bus line |4. A1 CPU Address bus line |
|5. A2 CPU Address bus line |6. A3 CPU Address bus line |
|7. A4 CPU Address bus line |8. A5 CPU Address bus line |
|9. A6 CPU Address bus line |10. GND Ground |
|11. A7 CPU Address bus line |12. A8 CPU Address bus line |
|13. A9 CPU Address bus line |14. A10 CPU Address bus line |
|15. A11 CPU Address bus line |16. A12 CPU Address bus line |
|17. A13 CPU Address bus line |18. A14 CPU Address bus line |
|19. GND Ground |20. A15 CPU Address bus line |
|21. D0 CPU Data bus line |22. D1 CPU Data bus line |
|23. D2 CPU Data bus line |24. D3 CPU Data bus line |
|25. D4 CPU Data bus line |26. D5 CPU Data bus line |
|27. D6 CPU Data bus line |28. D7 CPU Data bus line |
|29. GND Ground |30. GND Ground |
|31. B02,Phi2 CPU Phase 2 clock |32. GND Ground |
|33. NC Reserved |34. _RST Reset output |
|35. _IRQ Interrupt request |36. _RDY Ready input |
|37. NC Reserved |38. _EXTENB CPU External decoder Enable |
|39. NC Reserved |40. _REF Refresh cycle |
|41. _CAS Column Address Strobe |42. GND Ground |
|43. _MPD Math Pack (FP) Disable |44. _RAS Row Address Strobe |
|45. GND Ground |46. LR/_W Latched read/write |
|47. 800XL: NC. 600XL: +5V |48. 800XL: NC. 600XL: +5V |
|49. Audio input |50. GND Ground |
_=active low |
---- |
with information from: |
* [http://www.faqs.org/faqs/atari-8-bit/faq/] |
* [http://www.hardwarebook.info/] |
---- |
see [topic list] |