This page (revision-5) was last changed on 03-Feb-2023 15:21 by Florian Dingler 

This page was created on 11-Oct-2015 20:30 by Florian Dingler

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Version Date Modified Size Author Changes ... Change note
5 03-Feb-2023 15:21 737 bytes Florian Dingler to previous
4 21-Mar-2017 23:06 735 bytes Florian Dingler to previous | to last
3 10-Mar-2017 21:03 697 bytes Florian Dingler to previous | to last
2 11-Oct-2015 20:34 689 bytes Florian Dingler to previous | to last
1 11-Oct-2015 20:30 684 bytes Florian Dingler to last

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PACTL
PACTL

Version management

Difference between version and

At line 14 changed one line
To define the data direction of PORT A, set Bit 2 of PACTL to 0.
To define the data direction of PORT A, set Bit 2 of [PACTL] to 0. Then write a byte to [PORTA], where Bits set to 1 indicate WRITE and Bits set to 0 indicate READ. Normally [PORTA] set to %00000000 (=all input).
At line 16 removed 4 lines
Then write a byte to [PORTA], where Bits set to 1 indicate WRITE and Bits set to 0 indicate READ.
Normally set to %00000000 (=all input).
This page (revision-5) was last changed on 03-Feb-2023 15:21 by Florian Dingler  Top