SIO-Connector#
__________________________
/ \
/ 2 4 6 8 10 12 \
/ \
/ 1 3 5 7 9 11 13 \
/__________________________________\
| lower row | upper row |
|---|---|
| 1 Clock Input | 2 Clock Output |
| 3 Data Input | 4 Ground |
| 5 Data Output | 6 Ground |
| 7 _Command | 8 Motor control |
| 9 _Proceed | 10 +5V DC/Ready |
| 11 Audio Input | 12 +12V DC |
| 13 _Interrupt |
Notes:
- _=active low
- Pin 10: +5V DC not on 1200XL
- Pin 12: +12V DC on 400/800 only. 1400XL/1450XLD?
Joystick-Connector#
_________________________
\ /
\ 1 2 3 4 5 /
\ /
\ 6 7 8 9 /
\_______________/
| lower row | upper row |
|---|---|
| 1 Up | 6 Trigger |
| 2 Down | 7 +5V DC |
| 3 Left | 8 Ground |
| 4 Right | 9 Pot A |
| 5 Pot B |
5,9 see PADDL0-PADDL7
6 see STRIG0-STRIG3, also Light Pen Input, see LPENV, LPENH, (400 supports a light pen or 7. +5V light gun in port 4 only)
Monitor Connector#
3 o o 1
5 o o 4
o
2
5 PIN DIN 180° (DIN41524) FEMALE at the computer.
| Pin | Description |
|---|---|
| 1 | Composite Luminance (Composite Video on PAL 600XL) |
| 2 | Ground |
| 3 | Audio Output |
| 4 | Composite Video |
| 5 | Composite Chroma (not on 800XL (except "800XLF"), 1200XL; Ground on PAL 600XL) |
Power Connector#
not on 400, 800, 1200XL
7 o o 6
3 o o 1
5 o o 4
o
2
7 PIN DIN 'C' FEMALE at the computer.
| Pin | Description |
|---|---|
| 1 | +5V |
| 2 | Shield |
| 3 | Ground |
| 4 | +5V |
| 5 | Ground |
| 6 | +5V |
| 7 | Ground |
Power consumption
| Model | Current @ 5VDC |
|---|---|
| 130XE | 1.5A |
| 65XE | 1.0A |
| 800XE | 1.0A |
| XE | 1.0A |
| 600XL | 1.5A |
| 800XL | 1.5A |
Cartridge#
on all machines; "Left Cartridge" on 800A B C D E F H J K L M N P R S o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o 1 15
| upper row | lower row |
|---|---|
| 1. _S4 Chip Select--$8000 to $9FFF | A. RD4 ROM present- $8000 to $9FFF |
| 2. A3 CPU Address bus line | B. GND Ground |
| 3. A2 CPU Address bus line | C. A4 CPU Address bus line |
| 4. A1 CPU Address bus line | D. A5 CPU Address bus line |
| 5. A0 CPU Address bus line | E. A6 CPU Address bus line |
| 6. D4 CPU Data bus line | F. A7 CPU Address bus line |
| 7. D5 CPU Data bus line | H. A8 CPU Address bus line |
| 8. D2 CPU Data bus line | J. A9 CPU Address bus line |
| 9. D1 CPU Data bus line | K. A12 CPU Address bus line |
| 10. D0 CPU Data bus line | L. D3 CPU Data bus line |
| 11. D6 CPU Data bus line | M. D7 CPU Data bus line |
| 12. _S5 Chip Select--$A000 to $BFFF | N. A11 CPU Address bus line |
| 13. +5V | P. A10 CPU Address bus line |
| 14. RD5 ROM present--$A000 to $BFFF | R. _R/W CPU read/write |
| 15. _CCTL Cartridge control select | S. B02,Phi2 CPU Phase 2 clock |
Enhanced Cartridge Interface (ECI)/Expansion port (130XE, 800XE, & later 65XE)#
A B C D E F H o o o o o o o o o o o o o o 1 2 3 4 5 6 7
| upper row | lower row |
|---|---|
| A. Reserved | 1. _EXTSEL External Select |
| B. _IRQ Interrupt request | 2. _RST Reset output |
| C. _HALT Halt CPU | 3. _D1XX Chip select at area $D1xx |
| D. A13 CPU Address bus line | 4. _MPD Math Pack (FP) Disable |
| E. A14 CPU Address bus line | 5. Audio input |
| F. A15 CPU Address bus line | 6. _REF Refresh cycle |
| H. GND Ground | 7. +5V |
