This page (revision-9) was last changed on 03-Feb-2023 15:21 by Florian Dingler 

This page was created on 21-Mar-2010 20:28 by Florian Dingler

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Page revision history

Version Date Modified Size Author Changes ... Change note
9 03-Feb-2023 15:21 1 KB Florian Dingler to previous
8 19-Feb-2019 18:13 1 KB Florian Dingler to previous | to last
7 17-Feb-2019 22:02 1 KB Florian Dingler to previous | to last
6 27-Mar-2010 18:17 1 KB Florian Dingler to previous | to last
5 21-Mar-2010 21:51 1 KB Florian Dingler to previous | to last
4 21-Mar-2010 20:35 1 KB Florian Dingler to previous | to last
3 21-Mar-2010 20:33 708 bytes Florian Dingler to previous | to last
2 21-Mar-2010 20:31 554 bytes Florian Dingler to previous | to last
1 21-Mar-2010 20:28 284 bytes Florian Dingler to last

Page References

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AUDCTL
AUDCTL

Version management

Difference between version and

At line 8 changed 8 lines
|7| Makes the 17 bit poly counter into nine bit poly
|6| Clock channel one with 1.79 MHz
|5| Clock channel three with 1.79 MHz
|4| Join channels two and one (16 bit)
|3| Join channels four and three (16 bit)
|2| Insert high pass filter into channel one, clocked by channel two
|1| Insert high pass filter into channel two, clocked by channel four
|0| Switch main clock base from 64 KHz to 15 KHz to be done
|7| 0=17 bit poly counter \\1=9 bit polynomial noise
|6| 0=clock channel 1 with 64kHz\\1=Clock channel one with 1.79 MHz
|5| 0=clock channel 3 with 64kHz\\1=Clock channel three with 1.79 MHz
|4| 0=clock channel 2 with 64kHz\\1=Join channels two and one (16 bit)
|3| 0=clock channel 4 with 64kHz\\1=Join channels four and three (16 bit)
|2| 1=Insert high pass filter into channel one, clocked by channel two
|1| 1=Insert high pass filter into channel two, clocked by channel four
|0| 0=main clock base 64 KHz\\1=16 KHz main clock base
This page (revision-9) was last changed on 03-Feb-2023 15:21 by Florian Dingler  Top