This page (revision-9) was last changed on 03-Feb-2023 15:21 by Florian Dingler 

This page was created on 21-Mar-2010 20:28 by Florian Dingler

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Version Date Modified Size Author Changes ... Change note
9 03-Feb-2023 15:21 1 KB Florian Dingler to previous
8 19-Feb-2019 18:13 1 KB Florian Dingler to previous | to last
7 17-Feb-2019 22:02 1 KB Florian Dingler to previous | to last
6 27-Mar-2010 18:17 1 KB Florian Dingler to previous | to last
5 21-Mar-2010 21:51 1 KB Florian Dingler to previous | to last
4 21-Mar-2010 20:35 1 KB Florian Dingler to previous | to last
3 21-Mar-2010 20:33 708 bytes Florian Dingler to previous | to last
2 21-Mar-2010 20:31 554 bytes Florian Dingler to previous | to last
1 21-Mar-2010 20:28 284 bytes Florian Dingler to last

Page References

Incoming links Outgoing links
AUDCTL
AUDCTL

Version management

Difference between version and

At line 2 changed 2 lines
|Read|53768|$D208|ALLPOT| |all
|Write|53768|$D208|AUDCTL| |all
|Read|53768|$D208|ALLPOT|Audio control|all
|Write|53768|$D208|AUDCTL|Pot Port State|all
At line 5 changed 2 lines
!!!Write
to be done
!!!AUDCTL (Write)
AUDCTL is the option byte which affects all sound channels. This bit assignment is:
||Bit||Description
|7| 0=17 bit poly counter \\1=9 bit polynomial noise
|6| 0=clock channel 1 with 64kHz\\1=Clock channel one with 1.79 MHz (NTSC) or 1.77MHz (PAL)
|5| 0=clock channel 3 with 64kHz\\1=Clock channel three with 1.79 MHz (NTSC) or 1.77MHz (PAL)
|4| 0=clock channel 2 with 64kHz\\1=Join channels two and one (16 bit, with 2/4=MSB, 1/2=LSB)
|3| 0=clock channel 4 with 64kHz\\1=Join channels four and three (16 bit, with 2/4=MSB, 1/2=LSB)
|2| 1=Insert high pass filter into channel one, clocked by channel two
|1| 1=Insert high pass filter into channel three, clocked by channel four
|0| 0=main clock base 64 KHz\\1=16 KHz main clock base
At line 8 changed 2 lines
!!!Read
to be done
!!!ALLPOT (Read)
Shows if the readings of the pots are (already) valid.
||Bit||Paddle||Shadow||Register
|0|Paddle 0| [PADDL0]| [POT0]
|1|Paddle 1| [PADDL1]| [POT1]
|2|Paddle 2| [PADDL2]| [POT2]
|3|Paddle 3| [PADDL3]| [POT3]
|4|Paddle 4| [PADDL4]| [POT4]
|5|Paddle 5| [PADDL5]| [POT5]
|6|Paddle 6| [PADDL6]| [POT6]
|7|Paddle 7| [PADDL7]| [POT7]
If a bit equals zero (0), then the register value for that pot (e.g. Bit 0 = [POT0]) is valid; if the Bit is one (1), then the value is not (yet) valid, because the reading/scan is not finished yet or there is no paddle connected.
At line 12 changed one line
see also: [Controller topics|Controller_topics], [POTGO], [ALLPOT]
see also: [Controller topics|Controller_topics], [POTGO], [ALLPOT], [SKCTL]
At line 16 changed one line
next: [STIMER]
next: [STIMER|KBCODE],[KBCODE]
This page (revision-9) was last changed on 03-Feb-2023 15:21 by Florian Dingler  Top